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Design and Performance Analysis of a High-Speed Network Processor

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dc.contributor.advisor Rafiq, Prof. Dr. Md. Abdur
dc.contributor.author Islam, Md. Jahidul
dc.date.accessioned 2018-08-09T03:53:48Z
dc.date.available 2018-08-09T03:53:48Z
dc.date.copyright 2011
dc.date.issued 2011-08
dc.identifier.other ID 0803507
dc.identifier.uri http://hdl.handle.net/20.500.12228/234
dc.description This thesis is submitted to the Department of Electrical and Electronic Engineering, Khulna University of Engineering & Technology in partial fulfillment of the requirements for the degree of Master of Science in Electrical and Electronic Engineering, August 2011 en_US
dc.description Cataloged from PDF Version of Thesis.
dc.description Includes bibliographical references (pages 77-79).
dc.description.abstract Network processor is the key architecture of the recent communication technology. Most of the high performance network equipments especially routers, switches and traffic management systems are designed with network processor to processes their network packets. This research work introduces a design architecture for high-speed network packet processor and also analyzes its performance. There are two proposals in this thesis, first is the proposed hardware architecture of a high-speed network processor system and second is the proposed modified architecture of packet processing unit. A hierarchical 4 level layered processing architecture is developed for efficiently process the packets. To capture all traffic from a high-speed I/O interface without any loss a load-balancer with an efficient load distribution algorithm is implemented. High throughput pipelined memory architecture is also developed to minimize the rate of memory access time. The processor units have four basic operational tasks - parse, search, resolve and modify. To design the processing unit, the thesis provides some modification of the Task Optimized Processing core (TOPcore) technology and proposed a modified processing core architecture. This is a super-pipelined parallel architecture. The performance of the proposed network processor is evaluated for some real applications and compared with reference NPs. Results shows that the proposed architecture is efficient and provides better performance. Finally, the design is modeled and simulated in RT level using VHDL and then synthesized to schematic. The synthesis is done for both Xilinx Spartan3 and Actel ProASIC3 FPGA. Design requires very little FPGA logic while efficiently processing packet and implementation of green technology provides saving of power consumption at ideal condition. en_US
dc.description.statementofresponsibility Md. Jahidul Islam
dc.format.extent 79 pages
dc.language.iso en_US en_US
dc.publisher Khulna University of Engineering & Technology (KUET), Khulna, Bangladesh. en_US
dc.rights Khulna University of Engineering & Technology (KUET) thesis/ dissertation/internship reports are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission.
dc.subject High-Speed Network Processor en_US
dc.subject Network processor en_US
dc.subject Networking
dc.title Design and Performance Analysis of a High-Speed Network Processor en_US
dc.type Thesis en_US
dc.description.degree Master of Science in Electrical and Electronic Engineering
dc.contributor.department Department of Electrical and Electronic Engineering


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