Design and Performance Analysis of a High-Speed Network Processor

Abstract

Network processor is the key architecture of the recent communication technology. Most of the high performance network equipments especially routers, switches and traffic management systems are designed with network processor to processes their network packets. This research work introduces a design architecture for high-speed network packet processor and also analyzes its performance. There are two proposals in this thesis, first is the proposed hardware architecture of a high-speed network processor system and second is the proposed modified architecture of packet processing unit. A hierarchical 4 level layered processing architecture is developed for efficiently process the packets. To capture all traffic from a high-speed I/O interface without any loss a load-balancer with an efficient load distribution algorithm is implemented. High throughput pipelined memory architecture is also developed to minimize the rate of memory access time. The processor units have four basic operational tasks - parse, search, resolve and modify. To design the processing unit, the thesis provides some modification of the Task Optimized Processing core (TOPcore) technology and proposed a modified processing core architecture. This is a super-pipelined parallel architecture. The performance of the proposed network processor is evaluated for some real applications and compared with reference NPs. Results shows that the proposed architecture is efficient and provides better performance. Finally, the design is modeled and simulated in RT level using VHDL and then synthesized to schematic. The synthesis is done for both Xilinx Spartan3 and Actel ProASIC3 FPGA. Design requires very little FPGA logic while efficiently processing packet and implementation of green technology provides saving of power consumption at ideal condition.